• Self-synchronyzing over the whole Frequency Range
• Adjustable Data Threshold and Clock Phase
• Integrated Error Counter

The error analyzer detects bit errors contained in the connected input data stream. In combiantion with a Sympuls pattern generator it forms a complete bit error rate tester (BERT). Every single bit error contained in the input data stream is detected and counted in the internal error counter. The data threshold and clock phase adjustment allows a detailed analysis of the connected data signal, e.g. eye contour analysis.

The error analyzers are optionally available with an integrated clock recovery circuit operating gap-free at bit rates between 50 MBit/s and 11.3 Gbit/s.

Type	Data Rate		Patterns	Data Input			User Interface	Data Sheet
	min	max	PRBS 2n-1	Amplitude	Offset	Connector
SBF 44G	1 GBit/s	44 GBit/s	n= 7, 9, 11, 15, 23, 31	0.2 Vpp... 0.8 Vpp	±100 mV	50 Ω 2.92mm	Front Panel, USB
SBF 32G	1 GBit/s	32 GBit/s	n= 7, 9, 11, 15, 23, 31	0.1 Vpp... 0.8 Vpp	±100 mV	50 Ω 2.92mm	Front Panel, USB
SBF 28G	1 GBit/s	28 GBit/s	n= 7, 9, 11, 15, 23, 31	0.1 Vpp... 0.8 Vpp	±100 mV	50 Ω 2.92mm	Front Panel, USB
SBF 12G	0.1 GBit/s	14 GBit/s	n= 7, 9, 11, 15, 23, 31	0.05 Vpp... 0.8 Vpp	±100 mV	50 Ω SMA	Front Panel, USB
SBF 3000	50 MBit/s	3 GBit/s	n= 7, 9, 11, 15, 23, 31	0.05 Vpp... 0.8 Vpp	± 100 mV	50 Ω SMA	Front Panel, USB